This invention relates generally to semiconductor transistor devices, and more particularly to a high speed junction field effect transistor.
The use of junction field effect transistors (JFETs) in bipolar integrated circuits is known (BIFETs). One such transistor is disclosed in U.S. Pat. No. 4,176,368. Operating speed is an important characteristic of such a transistor. BIFET structures have included top and bottom gates with the top gate comprising a lightly doped region above the transistor channel region and with the top and bottom gates electrically connected through the semiconductor structure. U.S. Pat. No. 4,176,368 proposes a higher speed BIFET by forming a more heavily doped region in the lightly doped top gate between and separated from the source and drain regions of the transistor. The heavily doped region reduces the gate conductance from 5-15 kilo-ohms per square to a range of 500-1500 ohms per square.
JFETS having independent upper and lower gate contacts are known. The prior art teaches the use of barrier metals on the surface of the upper gate to prevent penetration of aluminum contacts into the underlying silicon material. Use of the barrier metal creates a thermal mismatch with the silicon leading to hysteresis effects during thermal cycling which degrade the device.